Preliminary calendar, subject to change!

Calendar

The Hardware Software Interface

Jan 21

Intro & What is Computer Architecture? [slides] [pdf]

Syllabus

Jan 22

No Lab

Jan 23

(re-)Introducing the HW-SW Interface [slides] [pdf]

H&P 1.3, 1.9

Jan 26

Data Representations & Assembly [slides] [pdf]

H&P A.1, A.2

Jan 28

Designing an Assembly Instruction [slides] [pdf]

S&L 1.2

Jan 29

Assembly Lab

Jan 30

Assembly Design, cont. [slides] [pdf]

H&P A.4, A.7 Check-In 1 in class HW1 Released

Feb 2

RISC v CISC [slides] [pdf]

TCftRISC

Last Day to Add Course!

Basic Processor Design

Feb 4

Hardware Principles [slides] [pdf]

TBD

Feb 5

Processor Emulator Gear-Up Lab

Feb 6

Building a Basic Processor (Part 1) [slides] [pdf]

TBD HW1 Part 1 due Tonight!

Feb 9

Building a Basic Processor (Part 2) [slides] [pdf]

TBD

Feb 11

Single Cycle Processor Control and Performance [slides] [pdf]

TBD

Feb 12

GDB Lab

Feb 13

Building a Pipelined CPU [slides] [pdf]

TBD Check-In 2 in class

Feb 16

Pipelined Processor (Part 2) [slides] [pdf]

TBD HW1 Part 2 due Tonight!

Feb 18

Pipeline Pitfalls and Hazards [slides] [pdf]

TBD

Feb 19

Intro to gem5 Lab

Feb 20

Managing Hazards [slides] [pdf]

TBD

Feb 23

Introducing Processor Control [slides] [pdf]

TBD

Memory Hierarchy

Feb 25

Memory Hierarchy Overview [slides] [pdf]

TBD HW1 Part 3 due Tonight! HW2 released

Feb 26

Cache Assignment Gear-Up Lab

Feb 27

No class!

Mar 2

[Storage Devices]

TBD Check-In 3 in class

Mar 4

[Cache Controller Construction (part 1)]

TBD

Mar 5

[Cache Performance Lab]

Mar 6

[Cache Controller Construction (part 2)]

TBD

Mar 9

[Understanding and Mitigating Misses]

TBD

Mar 11

[Coherence and Shared Caches]

TBD

Mar 12

ISA Leakage Gear-Up Lab

Today is the last day to drop course!

Mar 13

[Cache Security and Mitigations]

TBD Check-In 4 In-class

Mar 16

No class, spring break!

Mar 18

No class, spring break!

Mar 20

No class, spring break!

Mar 23

[Cache Attacks, cont.]

TBD HW3 Released

Mar 25

[Cache Attack Mitigations]

TBD

Mar 26

[Cache Performance Lab]

Mar 27

[Cache Attack Mitigations (cont.)]

TBD

Mar 30

[Recontextualizing the Memory System]

TBD

Advanced Processing (Control Instructions)

Apr 1

[Basic Control Instructions]

TBD

Apr 2

[Lab: TBD]

Apr 3

[Constructing a Data path for Control Instructions]

TBD

Apr 6

[The Negative Impact of Branching]

TBD CHECK-IN 5 IN CLASS

Apr 8

[Strategies to Handle Branches]

TBD

Apr 9

ISA Assignment Gear-Up

Apr 10

[Motivating Branch Prediction]

TBD

Apr 13

[Speculative Execution Attacks (Part 1)]

TBD

Apr 15

[Speculative Execution Attacks (Part 2)]

TBD

Apr 16

[Branch Prediction Lab]

Apr 17

[Advanced Instruction Level Parallelism]

TBD

Modern Computer Architectures

Apr 20

[Multicore Architectures]

TBD HW4 Released

Apr 22

[More Multicore Architectures]

TBD

Apr 23

[Ahmdahl’s Law Lab]

Apr 24

[A (Very Brief) Overview of GPUs]

TBD

Apr 27

[GPUs cont.]

TBD

Apr 29

[Green Computing]

Apr 30

Lab: TBD

May 1

[Topics in Computer Architecture]

TBD

May 3

[Topics in Architecture Security]

TBD

May 5

[Course Summary]

TBD